Fig. 6.4 Configuration Of Interrupt Control Register (Icr) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F
6.3.2 Function of Interrupt Control Register
The interrupt control register (ICR00 to ICR15) consists of the following bits with four types of functions.
• Interrupt level setting bits (IL2 to IL0)
• EI
2
OS enable bit (ISE)
• EI
2
OS channel select bits (ICS3 to ICS0)
• EI
2
OS status bits (S1 and S0)
n Configuration of interrupt control register (ICR)
Figure 6.4 shows the bit configuration of the interrupt control register (ICR).
At write to interrupt control register (ICR)
Address MSB
0000B0 to
H
ICS3
0000BF
H
At read from interrupt control register (ICR)
Address MSB
0000B0 to
H
—
0000BF
H
MSB : Most Significant Bit
LSB : Least Significant Bit
— : Unused
Remarks: 1. The ICS3 to ICS0 bits are only enabled at starting the EI
ISE bit to 1; when not starting EI
to ICS0 bits need not be set.
2. ICS1 and ICS0 are only enabled at writing, and S1 and S0 are only enabled at reading.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
ICS2 ICS1
— S1

Fig. 6.4 Configuration of Interrupt Control Register (ICR)

ICS0 ISE IL2
S0 ISE IL2
2
OS, set the ISE bit to 0. When not starting EI
6-10
LSB Initial value
IL1 IL0 00000111
LSB Initial value
IL1 IL0 --000111
2
OS. When starting EI
2
B
B
2
OS, set the
OS, the ICS3