ST STM32L4+ Series Reference Manual page 1738

Universal synchronous/asynchronous receiver transmitter (USART/UART)
The causes which contribute to the total deviation are:
•
DTRA: deviation due to the transmitter error (which also includes the deviation of the
transmitter's local oscillator)
•
DQUANT: error due to the baud rate quantization of the receiver
•
DREC: deviation of the receiver local oscillator
•
DTCL: deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
where
The USART receiver can receive data correctly at up to the maximum tolerated deviation
specified in
•
9-, 10- or 11-bit character length defined by the M bits in the USART_CR1 register
•
Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
•
Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.
•
Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register.
M bits
00
01
10
1738/2301
DTRA DQUANT DREC
+ +
DWU is the error due to sampling point deviation when the wakeup from low-
power mode is used.
when M[1:0] = 01:
when M[1:0] = 00:
when M[1:0] = 10:
t is the time between the detection of the start bit falling edge and the
WUUSART
instant when the clock (requested by the peripheral) is ready and reaching the
peripheral, and the regulator is ready.
Table 353, Table 354, depending on the following settings:
Table 353. Tolerance of the USART receiver when BRR [3:0] = 0000
OVER8 bit = 0
ONEBIT=0
3.75%
3.41%
4.16%
DTCL DWU <
+ +
t
WUUSART
-------------------------- -
DWU
=
11 × Tbit
t
WUUSART
-------------------------- -
DWU =
10 × Tbit
t
WUUSART
-------------------------- -
DWU =
9 Tbit ×
ONEBIT=1
4.375%
3.97%
4.86%
RM0432 Rev 6
USART receiver tolerance
OVER8 bit = 1
ONEBIT=0
2.50%
2.27%
2.77%
RM0432
ONEBIT=1
3.75%
3.41%
4.16%