ST STM32L4+ Series Reference Manual page 1747

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Case 1: break occurring after an Idle

Case 2: break occurring while data is being received

USART synchronous mode

The synchronous master mode is selected by programming the CLKEN bit in the

USART_CR2 register to '1'. In synchronous mode, the following bits must be kept cleared:

LINEN bit in the USART_CR2 register,

SCEN, HDSEL and IREN bits in the USART_CR3 register.

In this mode, the USART can be used to control bidirectional synchronous serial

communications in master mode. The SCLK pin is the output of the USART transmitter

clock. No clock pulses are sent to the SCLK pin during start bit and stop bit. Depending on

the state of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated

during the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is

used to select the clock polarity, and the CPHA bit in the USART_CR2 register is used to

select the phase of the external clock (see

During the Idle state, preamble and send break, the external SCLK clock is not activated.

In synchronous master mode, the USART transmitter operates exactly like in asynchronous

mode. However, since SCLK is synchronized with TX (according to CPOL and CPHA), the

data on TX is synchronous.

In synchronous master mode, the USART receiver operates in a different way compared to

asynchronous mode. If RE is set to 1, the data are sampled on SCLK (rising or falling edge,

depending on CPOL and CPHA), without any oversampling. A given setup and a hold time

must be respected (which depends on the baud rate: 1/16 bit time).

Universal synchronous/asynchronous receiver transmitter (USART/UART)

Figure 500. Break detection in LIN mode vs. Framing error detection

RM0432 Rev 6

data 2 (0x55)

data 3 (header)

data 2 (0x55)

data 3 (header)

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