ST SPC560P34 Manuals

Manuals and User Guides for ST SPC560P34. We have 1 ST SPC560P34 manual available for free PDF download: Reference Manual

ST SPC560P34 Reference Manual

ST SPC560P34 Reference Manual (936 pages)

32-bit MCU on the embedded Power Architecture

Brand: ST | Category: Microcontrollers | Size: 7 MB

Table of Contents

Table of Contents
2
Preface

45
- Overview
  45
- Audience
  45
- Chapter Organization and Device-Specific Information
  45
- References
  45
Introduction

46
SPC560P40/34 Memory Map

69
- Table 3. Memory Map
  69
Signal Description

72
Clock Description

91
Clock Generation Module (MC_CGM)

116
Mode Entry Module (MC_ME)

136
Power Control Unit (MC_PCU)

184
- Introduction
  184
  - Overview
    184
  - Features
    184
  - Figure 66. MC_PCU Block Diagram
    184
- External Signal Description
  185
- Memory Map and Register Definition
  185
Reset Generation Module (MC_RGM)

187
Interrupt Controller (INTC)

208
System Status and Configuration Module (SSCM)

240
System Integration Unit Lite (SIUL)

248
E200Z0 and E200Z0H Core

270
- Overview
  270
- Features
  270
  - Microarchitecture Summary
    271
  - Figure 116. E200Z0 Block Diagram
    272
  - Figure 117. E200Z0H Block Diagram
    273
- Core Registers and Programmer's Model
  275
- Instruction Summary
  278
- Figure 120. E200 User Mode Program Model
  278
Peripheral Bridge (PBRIDGE)

279
- Introduction
  279
  - Block Diagram
    279
  - Overview
    279
  - Modes of Operation
    279
  - Figure 121. PBRIDGE Interface
    279
- Functional Description
  280
  - Access Support
    280
  - General Operation
    280
Crossbar Switch (XBAR)

281
- Introduction
  281
- Block Diagram
  281
- Table 110. Device XBAR Switch Ports
  281
- Figure 122. XBAR Block Diagram
  281
- Overview
  282
- Features
  282
- Modes of Operation
  282
  - Normal Mode
    282
  - Debug Mode
    282
- Functional Description
  282
  - General Operation
    283
  - Master Ports
    283
  - Slave Ports
    284
  - Priority Assignment
    284
  - Arbitration
    284
  - Table 111. Hardwired Bus Master Priorities
    284
Error Correction Status Module (ECSM)

286
Internal Static RAM (SRAM)

308
- Introduction
  308
- SRAM Operating Mode
  308
- Module Memory Map
  308
- Register Descriptions
  308
- SRAM ECC Mechanism
  308
- Functional Description
  310
- Initialization and Application Information
  310
Flash Memory

311
Enhanced Direct Memory Access (Edma)

382
DMA Channel Mux (DMA_MUX)

424
Functional Safety

737
- Figure 419. Register Protection Memory Diagram
  738
- Features
  738
Wakeup Unit (WKPU)

776
Boot Assist Module (BAM)

806
- Figure 479. Boot Mode Selection
  807
Voltage Regulators and Power Supplies

836
IEEE 1149.1 Test Access Port Controller (JTAGC)

841

Advertisement

Advertisement

Related Products

ST Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

More ST Manuals