ST STM32G0 1 Series Reference Manual page 992

Inter-integrated circuit (I2C) interface
Bit 11 PECERR: PEC Error in reception
Note: This bit is cleared by hardware when PE=0.
Bit 10 OVR: Overrun/Underrun (slave mode)
Note: This bit is cleared by hardware when PE=0.
Bit 9 ARLO: Arbitration lost
Note: This bit is cleared by hardware when PE=0.
Bit 8 BERR: Bus error
Note: This bit is cleared by hardware when PE=0.
Bit 7 TCR: Transfer Complete Reload
Note: This bit is cleared by hardware when PE=0.
Bit 6 TC: Transfer Complete (master mode)
Note: This bit is cleared by hardware when PE=0.
Bit 5 STOPF: Stop detection flag
It is cleared by software by setting the STOPCF bit.
Note: This bit is cleared by hardware when PE=0.
Bit 4 NACKF: Not Acknowledge received flag
Note: This bit is cleared by hardware when PE=0.
Bit 3 ADDR: Address matched (slave mode)
Note: This bit is cleared by hardware when PE=0.
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This flag is set by hardware when the received PEC does not match with the PEC register
content. A NACK is automatically sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Refer to Section 32.3: I2C
This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun
error occurs. It is cleared by software by setting the OVRCF bit.
This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the
ARLOCF bit.
This flag is set by hardware when a misplaced Start or STOP condition is detected whereas
the peripheral is involved in the transfer. The flag is not set during the address phase in slave
mode. It is cleared by software by setting BERRCF bit.
This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is
cleared by software when NBYTES is written to a non-zero value.
This flag is only for master mode, or for slave mode when the SBC bit is set.
This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been
transferred. It is cleared by software when START bit or STOP bit is set.
This flag is set by hardware when a STOP condition is detected on the bus and the
peripheral is involved in this transfer:
– either as a master, provided that the STOP condition is generated by the peripheral.
– or as a slave, provided that the peripheral has been addressed previously during
this transfer.
This flag is set by hardware when a NACK is received after a byte transmission. It is cleared
by software by setting the NACKCF bit.
This bit is set by hardware as soon as the received slave address matched with one of the
enabled slave addresses. It is cleared by software by setting ADDRCF bit.
implementation.
RM0444 Rev 5
RM0444