Clock Selection; Figure 86. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32F205 series Reference Manual

RM0033
13.3.4

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin
•
External clock mode2: external trigger input ETR
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, the user can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Using one timer as prescaler for another timer
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 86
without prescaler.
CEN=CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
shows the behavior of the control circuit and the upcounter in normal mode,

Figure 86. Control circuit in normal mode, internal clock divided by 1

Internal clock
UG
CNT_INIT
31
Advanced-control timers (TIM1 and TIM8)
for more details.
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