Table 82. Adc Register Map And Reset Values (Common Adc Registers) - ST STM32F423 Reference Manual

RM0430
Offset Register
ADC_SQR3
0x34
Reset value
ADC_JSQR
0x38
Reset value
ADC_JDR1
0x3C
Reset value
ADC_JDR2
0x40
Reset value
ADC_JDR3
0x44
Reset value
ADC_JDR4
0x48
Reset value
ADC_DR
0x4C
Reset value

Table 82. ADC register map and reset values (common ADC registers)

Offset Register
ADC_CSR
0x00
Reset value
ADC_CCR
0x04
Reset value
Refer to
Table 81. ADC register map and reset values (continued)
0 0 0 0 0 0 0
0
Section 2.2.2 on page 58
Regular channel sequence SQx_x bits
0 0 0 0 0 0 0 0 0
JL[1:0] Injected channel sequence JSQx_x bits
0 0 0 0 0 0 0 0
0 0
0 0
0 0
0 0
0 0
0
for the register boundary addresses.
RM0430 Rev 8
Analog-to-digital converter (ADC)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
JDATA[15:0]
0 0 0 0 0 0 0 0 0
JDATA[15:0]
0 0 0 0 0 0 0 0 0
JDATA[15:0]
0 0 0 0 0 0 0 0 0
JDATA[15:0]
0 0 0 0 0 0 0 0 0
Regular DATA[15:0]
0 0 0 0 0 0 0 0 0
0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
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