Table 81. Dma Register Map And Reset Values - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Direct memory access controller (DMA)
Offset
Register
DMA_CNDTR7
0x084
Reset value
DMA_CPAR7
0x088
Reset value
DMA_CMAR7
0x08C
Reset value
Refer to
478/1454
Table 81. DMA register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 2.6
for the register boundary addresses.
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
MA[31:0]
0
0
0
0
0
0
0
0
0
RM0453 Rev 2
NDT[17:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0453
0
0
0
0
0 0
0
0
0
0
0 0
0
0
0
0
0 0

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