Sleep Mode; Clearing Sleep Mode - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Sleep Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR

are both cleared to 0, the CPU will enter sleep mode. In sleep mode, CPU operation stops but the

contents of the CPU's internal registers are retained. Other supporting modules (excluding some

functions) do not stop.

Sleep mode is cleared by any interrupt, or with the 5(6 pin.

Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and

interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled,

or if interrupts other than NMI have been masked by the CPU.

Clearing with the 5(6

5(6 Pin: When the 5(6 pin is driven low, the reset state is entered. When the

5(6 pin is driven high after the prescribed reset input period, the CPU begins reset exception

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