Exception-Handling State - Hitachi H8S/2199 Hardware Manual

2.8.3

Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) Types of Exception Handling and Their Priority
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14
indicates the types of exception handling and their priority. Trap instruction exception
handling is always accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in
SYSCR.
Table 2.14 Exception Handling Types and Priority
Priority Type of Exception
High Reset
Interrupt
Trap instruction
Low
Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
2. Trap instruction exception handling is always accepted in the program execution state.
(2) Reset Exception Handling
After the 5(6 pin has gone low and the reset state has been entered, when 5(6 goes high
again, reset exception handling starts. When reset exception handling starts the CPU fetches a
start address (vector) from the exception vector table and starts program execution from that
address. All interrupts, including NMI, are disabled during reset exception handling and after
it ends.
(3) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack
pointer (ER7) and pushes the program counter and other control registers onto the stack. Next,
the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU
fetches a start address (vector) from the exception vector table and program execution starts
from that start address.
Rev. 1.0, 02/00, page 56 of 1141
Detection Timing
Synchronized with
clock
End of instruction
execution or end of
exception-handling
*1
sequence
When TRAPA
instruction is executed
Start of Exception Handling
Exception handling starts immediately
after a low-to-high transition at the
5(6 pin, or when the watchdog timer
overflows
When an interrupt is requested,
exception handling starts at the end
of the current instruction or current
exception-handling sequence
Exception handling starts when a trap
(TRAPA) instruction is executed
*2