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2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the
access timing for the on-chip supporting modules.
φ
Internal address bus
Internal read signal
Read access
Internal data bus
Internal write signal
Write access
Internal data bus
Rev. 1.0, 02/00, page 60 of 1141
Figure 2.19 On-Chip Supporting Module Access Cycle
Bus cycle
T1
Address
Read data
Write data
T2
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