ARM DSTREAM-PT Reference Manual
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ARM DSTREAM-PT Reference Manual

System and interface design
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Arm
DSTREAM-PT
®
Version 1.0
System and Interface Design Reference Guide
Copyright © 2019 Arm Limited or its affiliates. All rights reserved.
101714_0100_02_en

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  • Page 1 DSTREAM-PT ® Version 1.0 System and Interface Design Reference Guide Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 101714_0100_02_en...

  • Page 2: Copyright © 2019 Arm Limited Or Its Affiliates. All Rights Reserved

    Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 3 This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

  • Page 4: Table Of Contents

    Arm JTAG 20 connector ..................2-35 CoreSight 10 connector ..................2-36 ™ CoreSight 20 connector ..................2-37 ™ TI JTAG 14 connector ....................2-39 Mictor 38 connector ....................2-40 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 5 Overview of high-speed design ................3-52 JTAG port buffering ....................3-55 Series termination ....................3-58 Parallel trace modeling .................... 3-59 Target design checklist .................... 3-60 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 6 Arm JTAG 20 connector pinout ....................2-35 Figure 2-2 CoreSight 10 connector pinout ....................2-36 Figure 2-3 CoreSight 20 connector pinout ....................2-37 Figure 2-4 TI JTAG 14 connector pinout ....................2-39 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 7 Figure 3-7 Daisy-chained JTAG connection without buffers ..............3-55 Figure 3-8 Daisy-chained JTAG connection with TCK buffers ..............3-56 Figure 3-9 Fully buffered JTAG connection ..................... 3-56 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 8 MIPI 60 pinout table ....................... 2-47 Table 2-11 User I/O pinout table ......................2-50 Table 3-1 Typical series terminating resistor values ................3-58 Table 3-2 Target design checklist ......................3-60 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 9 Preface This preface introduces the Arm DSTREAM-PT System and Interface Design Reference Guide. ® It contains the following: • About this book on page 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 10: Preface

    DSTREAM-ST has an Arm JTAG 20 connector, a CoreSight 20 connector, an auxiliary connector, and a user I/O connector. Chapter 3 Target board design When you design a target board to connect to the DSTREAM-PT system, you must consider the rules that are discussed in this chapter. Glossary...

  • Page 11: Table

    A concise explanation of your comments. Arm also welcomes general suggestions for additions and improvements. Note Arm tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. Other information •...
  • Page 12 Chapter 1 Debug and trace interface The Arm debug and trace interface enables powerful software debug and optimization on an Arm processor-based target system. It is based on the IEEE 1149.1 (JTAG) interface coupled with various additional signals. This chapter introduces these signals and describes their use within the interface.

  • Page 13: Jtag Signals

    1.1 JTAG signals JTAG signals Most Arm-based devices are physically equipped with several pins that are dedicated to debug and test purposes. Four of these pins make up the IEEE 1149.1 interface, also known as the JTAG interface. This interface is often used for boundary-scan testing during the manufacture of printed circuit boards. The interface also provides a useful way to access one or more cores and other components in a device, while running its application software.

  • Page 14: Figure 1-2 Chained Jtag Connection

    1149.1 (JTAG) specification. TDI and TMS are set up by the DSTREAM-PT system on the falling edge of TCK. These signals are then sampled by the target device on the rising edge of TCK. The target device must set up its TDO signal when it detects the falling edge of TCK which, in turn, will be sampled by the DSTREAM-PT system on the next rising edge of TCK.

  • Page 15: Figure 1-3 Jtag Timing Diagram

    Since all signals are set up on the falling edge of TCK and sampled on the rising edge, the effective setup and hold times for the target device and DSTREAM-PT system are approximately Tclk/2. Issues with signal timing can usually be resolved by decreasing the TCK frequency. Decreasing the TCK frequency increases the setup and hold times.

  • Page 16: Figure 1-4 Basic Jtag Port Synchronizer

    Chain Shift En RTCK TAP Ctrl CKEN State nCLR nCLR nCLR Machine nTRST nRESET Figure 1-6 JTAG port synchronizer for single rising-edge D-type ASIC design rules 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 1-16 Non-Confidential...

  • Page 17: Figure 1-7 Timing Diagram For The D-Type Jtag Synchronizer

    RTCK and TDO signals so that they only change state at the edges of TCK. TCKRisingEn TCKFallingEn RTCK TAPC State Figure 1-7 Timing diagram for the D-type JTAG synchronizer 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 1-17 Non-Confidential...

  • Page 18: Return Clock (Rtck) Signal

    Adaptive clocking mode is not recommended unless the target design requires it. • Adaptive clocking can be enabled using the configuration settings in Arm Development Studio. For more information, see Debug Hardware configuration in the Arm Development Studio User Guide.

  • Page 19: Reset Signals

    TAP controller state is changed. It is expected that the assertion of the nSRST line by the DSTREAM-PT system will cause a warm reset of the target system. If the nSRST line triggers a full, Power On Reset (POR), then the debug connection might be lost.

  • Page 20: Figure 1-8 Example Reset Circuit

    Power On Reset (POR) input, any voltage monitoring devices would typically connect to that instead. If the target device is equipped with internal voltage monitoring circuitry, external monitoring devices can be omitted. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 1-20 Non-Confidential...

  • Page 21: Run-Control Signals

    Debug Request (DBGRQ) The Debug Request (DBGRQ) pin stops the target processor and puts it into its debug state. Arm recommends that this signal is no longer used. It can be left open on the target board. Warning If the signal is used, it must be pulled on the target.

  • Page 22: Serial Wire Debug (Swd) Signals

    Figure 1-9 SWD timing diagrams The debug unit: • Writes data to SWDIO on the falling edge of SWCLK. • Reads data from SWDIO on the rising edge of SWCLK. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 1-22 Non-Confidential...
  • Page 23 T[is] Input setup time that is required between SWDIO and rising edge SWCLK. T[ih] Input hold time that is required between SWDIO and rising edge SWCLK. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 1-23 Non-Confidential...

  • Page 24: Trace Signals

    Some target devices can output high-bandwidth parallel trace data while the target application is running. Capturing this data and decoding it in Arm Development Studio allows you to examine the sequence of instructions, and changes in data, around a given point or trigger.

  • Page 25: Figure 1-10 Traceclk Timing Diagram

    TRACEDATA and TRACECLK outputs close to the target device. The value of these resistors, added to the impedance of the driver, must be approximately equal to 50Ω. To achieve the maximum data rate, Arm recommends using the short 20-way 0.05” pitch ribbon cable.

  • Page 26: Target Voltage Reference (Vtref) Signals

    To work with debug and trace interfaces on differing voltage rails, the DSTREAM-ST unit supports separate debug and trace voltage domains. VTREF When using either the CoreSight 20 or Arm JTAG 20 connector, only one voltage domain is supported. The voltage domain is determined using the VTREF signal. DEBUG_VTREF When using the Mictor adapter, or optional MIPI-34 or MIPI-60 adapters, the voltage domain of the debug signals is determined using the DEBUG_VTREF signal.

  • Page 27: Figure 1-11 Target Interface Logic Levels

    Vin(th) VTREF (V) Figure 1-11 Target interface logic levels The input and output characteristics of the DSTREAM-PT system are compatible with logic levels from TTL-compatible, or CMOS logic in target systems. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved.

  • Page 28: I/O Diagrams For Dstream-Pt Signals

    TCK signal The TCK output signal is similar to a standard output signal, but also has a switchable capacitor, forming a T-filter, which can reduce the TCK slew-rate. Enabling this filter is not currently supported in Arm Development Studio. 16.5R 16.5R...

  • Page 29: Figure 1-15 Trace Signals

    VTREF/2 through 50Ω resistors. These resistors prevent signals from being reflected back to the target system, increasing signal integrity and the maximum data rate. Disabling the input terminations is not currently supported in Arm Development Studio. VTREF/2 VTREF/2...

  • Page 30: Typical Swd Circuit

    To improve signal integrity, it is good practice to provide an impedance-matching resistor on the SWDIO and SWO outputs of the processor. The value of these resistors, added to the impedance of the driver, must be approximately equal to 50Ω. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 1-30 Non-Confidential...

  • Page 31: Typical Jtag Circuit

    To improve signal integrity, it is good practice to provide an impedance matching resistor on the TDO and RTCK outputs of the processor. The value of these resistors, added to the impedance of the driver, must be approximately equal to 50Ω. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 1-31 Non-Confidential...
  • Page 32 To adapt debug connectors for other target connectors, you can use cables and adapter boards. Some of these cables and adapter boards are supplied with the debug unit. Others can be requested from Arm. For a list of provided adapters, see the Arm DSTREAM-PT Getting Started Guide.
  • Page 33 2 Target interface connectors • 2.11 User I/O connector on page 2-50. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 2-33 Non-Confidential...

  • Page 34: Target Connector Selection Guide

    When choosing a debug or trace connector to design into a target board, there are many connector attributes to consider. The connector attributes are: Table 2-1 Connector attributes Connector Arm JTAG 20 CoreSight 10 CoreSight 20 TI JTAG 14 MICTOR 38 MIPI 34 MIPI 60 JTAG supported SWD supported SWO trace supported Parallel trace supported...

  • Page 35: Arm Jtag 20 Connector

    2.2 Arm JTAG 20 connector Arm JTAG 20 connector The Arm JTAG 20 connector is a 20-way 2.54mm pitch box header which supports JTAG debug, Serial Wire Debug, and SWO trace. To use this connector with DSTREAM-ST, use the Arm JTAG 20 debug cable supplied in the box contents.

  • Page 36: 10 Connector

    Warning Using a non-shrouded header on the target board can lead to short-circuits or signal contention. To ensure the correct polarity and position, Arm recommends that you use a fully shrouded box header. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved.

  • Page 37: 20 Connector

    The CoreSight 20 connector is a 20-way 1.27mm pitch box header which supports JTAG debug, Serial Wire Debug, SWO trace, and up to 4-bit wide continuous-mode TPIU trace. To use CoreSight 20 connector with the DSTREAM-PT system, use the CoreSight 20 debug cable supplied in the box contents.

  • Page 38: Arm Coresight 20 Pinout Table (Dstreamcs20=1)

    Warning Using a non-shrouded header on the target board can lead to short-circuits or signal contention. To ensure the correct polarity and position, Arm recommends that you use a fully shrouded box header. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved.

  • Page 39: Ti Jtag 14 Connector

    The Texas Instruments (TI) JTAG 14 connector is a 14-way 2.54mm pitch box header which supports JTAG debug, Serial Wire Debug, and SWO trace. To use this connector with DSTREAM-ST, the supplied TI JTAG 14 adapter must be used with the Arm JTAG 20 debug cable.

  • Page 40: Mictor 38 Connector

    To use this connector with DSTREAM-ST, the supplied 4-bit Mictor adapter must be used in conjunction with both the Arm JTAG 20 debug cable and the CoreSight 20 debug cable. To use this connector with DSTREAM-PT, the supplied 16-bit Mictor adapter must be used in conjunction with the MIPI-60 cable.
  • Page 41 1. The EXTTRIG signal is deprecated and not supported by Arm Development Studio. 2. Although the Arm CoreSight specification only supports a single VTREF (on pin 12), DSTREAM- ST can support separate debug and trace VTREFs. If only TRACE_VTREF is powered, the DSTREAM-ST assumes that both debug and trace are to operate at that voltage.

  • Page 42: Dual Mictor Connectors

    If you do not solder-paste on the same side of the PCB as the connector, it might cause mechanical or signal integrity issues. Typically, the sockets used are a 2-767004-2 from TE Connectivity. To use these connectors with DSTREAM-PT, the supplied 32-bit Mictor adapter must be used in conjunction with the MIPI-60 cable. 101714_0100_02_en Copyright ©...

  • Page 43: Figure 2-6 Dual Mictor Connector Pinout

    2 Target interface connectors 2.7 Dual Mictor connectors MICTOR B 1.35" (34.29mm) MICTOR A Figure 2-6 Dual Mictor connector pinout 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 2-43 Non-Confidential...

  • Page 44: Mictor B Pinout Table

    TRACEDATA[24] 38 TRACEDATA[16] Note 1. These signals are not used by Arm debug units. To maintain compatibility with other debug units, connect the signals to the appropriate power rails. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved.

  • Page 45: Mipi 34 Connector

    MIPI 34 pinout table Table 2-9 MIPI 34 pinout table Pin Signal name Pin Signal name DEBUG_VTREF 2 TMS/SWDIO TCK/SWCLK TDO/SWO Key (NC) nSRST GND (1) RTCK 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 2-45 Non-Confidential...
  • Page 46 Warning Using a non-shrouded header on the target board can lead to short-circuits or signal contention. To ensure the correct polarity and position, Arm recommends that you use a fully shrouded box header. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved.

  • Page 47: Mipi 60 Connector

    The MIPI 60 connector is a 60-way 0.5mm pitch socket which supports JTAG debug, Serial Wire Debug, SWO trace, and up to 32-bit wide continuous-mode TPIU trace. Typically, the socket is a QTH-030-01-L-D-A from Samtec. To use this connector with DSTREAM-PT, use the MIPI debug cable supplied in the box contents. Note •...
  • Page 48 Note • DSTREAM-ST only supports one channel of parallel trace. • Pins marked as RESERVED might be internally connected in DSTREAM-ST, but are not currently supported. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 2-48 Non-Confidential...

  • Page 49: Auxiliary (Aux) Connector

    (for example, 32-bit, HSSTP, or PCIe). Warning This connector is not intended for user I/O. Do not attempt to connect anything other than Arm DSTREAM-ST compatible probes. This connector is not compatible with older RealView Trace (RVT) probes.

  • Page 50: User I/O Connector

    The user I/O connector is a standard 10-way 2.54mm pitch box header on the rear of DSTREAM-ST. Figure 2-9 User I/O connector pinout Note When connecting and disconnecting the user I/O port, Arm recommends that all equipment is powered- down. User I/O pinout table...
  • Page 51 Chapter 3 Target board design When you design a target board to connect to the DSTREAM-PT system, you must consider the rules that are discussed in this chapter. It contains the following sections: • 3.1 Overview of high-speed design on page 3-52.

  • Page 52: Overview Of High-Speed Design

    3.1 Overview of high-speed design Overview of high-speed design When designing a target board that will be connected to a DSTREAM-PT system, it is important to use good digital design practice to achieve high Signal Integrity (SI). While many target boards already take SI into consideration for trace signals, it is also important to use the same design methodology for the debug signals.

  • Page 53: Figure 3-3 Long Stub Causing False Edges

    When the return path is interrupted, it causes distortion and some loss in the signal. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 3-53 Non-Confidential...
  • Page 54 There are several ways to minimize electric and magnetic field coupling: — Space the signal tracks further apart. Arm recommends to keep adjacent signals at least three times further apart than they are from the nearest plane (the 3W rule).

  • Page 55: Jtag Port Buffering

    Figure 3-6 JTAG connection with TDO buffer Sometimes, two or more devices are chained together in the target system: Debug Target Connector Device Target Device Figure 3-7 Daisy-chained JTAG connection without buffers 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 3-55 Non-Confidential...

  • Page 56: Figure 3-8 Daisy-Chained Jtag Connection With Tck Buffers

    This causes some skew between the TDI, TMS, and TCK signals. To correct this skew, use the same type of buffers on the TDI, TMS, and TCK signals. For example: Debug Target Connector Device Target Device Figure 3-9 Fully buffered JTAG connection 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved. 3-56 Non-Confidential...
  • Page 57 For added noise rejection, Schmitt buffers can be used instead of standard buffers. • Arm recommends you use buffers with a drive strength of 24mA or above. • For any buffered signal, place the signal pull-up or pull-down resistor at the input-side of the buffer.

  • Page 58: Series Termination

    The receiver observes a perfect 100% logic transition, without any overshoot or ringing. To ensure that a reliable signal is delivered to the DSTREAM-ST unit, Arm recommends that all outputs from the target system are simulated, and, if necessary, series terminated. Some overshoot or undershoot is acceptable, but Arm recommends ensuring this is kept less than ~0.5V.

  • Page 59: Parallel Trace Modeling

    All other parasitics and traces within the DSTREAM-ST are negligible for most purposes. Note To achieve good signal integrity, Arm recommends using series termination resistors on all target outputs. 101714_0100_02_en Copyright © 2019 Arm Limited or its affiliates. All rights reserved.

  • Page 60: Target Design Checklist

    3 Target board design 3.5 Target design checklist Target design checklist To ensure your target design is compatible with the DSTREAM-ST unit or DSTREAM-PT system, your answer to each applicable question in this checklist must be ‘Yes’. Note Not all questions are applicable to every target design.

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