ARM Cortex-M3 Technical Reference Manual page 75

Name of register
.
Irq 224 to 239 Clear Enable Register
Irq 0 to 31 Set Pending Register
.
.
.
Irq 224 to 239 Set Pending Register
Irq 0 to 31 Clear Pending Register
.
.
.
Irq 224 to 239 Clear Pending Register
Irq 0 to 31 Active Bit Register
.
.
.
Irq 224 to 239 Active Bit Register
Irq 0 to 3 Priority Register
.
.
.
Irq 236 to 239 Priority Register
CPUID Base Register
Interrupt Control State Register
Vector Table Offset Register
ARM DDI 0337G
Unrestricted Access
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Non-Confidential
Table 3-1 NVIC registers (continued)
Type
.
Read/write
Read/write
.
.
.
Read/write
Read/write
.
.
.
Read/write
Read-only
.
.
.
Read-only
Read/write
.
.
.
Read/write
Read-only
Read/write or read-only
Read/write
System Control
Address Reset value
. .
0xE000E19C 0x00000000
0xE000E200 0x00000000
. .
. .
. .
0xE000E21C 0x00000000
0xE000E280 0x00000000
. .
. .
. .
0xE000E29C 0x00000000
0xE000E300 0x00000000
. .
. .
. .
0xE000E31C 0x00000000
0xE000E400 0x00000000
. .
. .
. .
0xE000E4EC 0x00000000
0xE000ED00 0x412FC230
0xE000ED04 0x00000000
0xE000ED08 0x00000000
3-3