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Nested Vectored Interrupt Controller
Table 8-17 Application Interrupt and Reset Control Register bit assignments (continued)
Bits
Field
[7:3]
-
[2]
SYSRESETREQ
[1]
VECTCLRACTIVE
[0]
VECTRESET
8-24
Function
PRIGROUP 0
Split of pre-emption priority from subpriority
1
7.1 indicates seven bits of pre-emption priority, one bit of subpriority
2
6.2 indicates six bits of pre-emption priority, two bits of subpriority
3
5.3 indicates five bits of pre-emption priority, three bits of subpriority
4
4.4 indicates four bits of pre-emption priority, four bits of subpriority
5
3.5 indicates three bits of pre-emption priority, five bits of subpriority
6
2.6 indicates two bits of pre-emption priority, six bits of subpriority
7
1.7 indicates one bit of pre-emption priority, seven bits of subpriority
0.8 indicates no pre-emption priority, eight bits of subpriority.
PRIGROUP field is a binary point position indicator for creating subpriorities for
exceptions that share the same pre-emption level. It divides the PRI_n field in the
Interrupt Priority Register into a pre-emption level and a subpriority level. The binary
point is a left-of value. This means that the PRIGROUP value represents a point starting
at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0.
The lowest value might not be 0 depending on the number of bits allocated for priorities,
and implementation choices.
Reserved.
Causes a signal to be asserted to the outer system that indicates a reset is requested.
Intended to force a large system reset of all major components except for debug. Setting
this bit does not prevent Halting Debug from running.
Clear active vector bit:
1 = clear all state information for active NMI, fault, and interrupts
0 = do not clear.
It is the responsibility of the application to reinitialize the stack.
The VECTCLRACTIVE bit is for returning to a known state during debug. The
VECTCLRACTIVE bit self-clears.
IPSR is not cleared by this operation. So, if used by an application, it must only be used
at the base level of activation, or within a system handler whose active bit can be set.
System Reset bit. Resets the system, with the exception of debug components:
1 = reset system
0 = do not reset system.
The VECTRESET bit self-clears. Reset clears the VECTRESET bit.
For debugging, only write this bit when the core is halted.
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