ARM Cortex-M3 Technical Reference Manual page 259

Name
Trace Control Register
Integration Write
Integration Read
Integration Mode Control
Lock Access Register
Lock Status Register
PID4
PID5
PID6
PID7
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
ARM DDI 0337G
Unrestricted Access
Type Address
Read/write
0xE0000E80
Write-only 0xE0000EF8
Read-only
0xE0000EFC
Read/write
0xE0000F00
Write-only
0xE0000FB0
Read-only 0xE0000FB4
Read-only 0xE0000FD0
Read-only
0xE0000FD4
Read-only
0xE0000FD8
Read-only
0xE0000FDC
Read-only
0xE0000FE0
Read-only
0xE0000FE4
Read-only 0xE0000FE8
Read-only 0xE0000FEC
Read-only
0xE0000FF0
Read-only
0xE0000FF4
Read-only
0xE0000FF8
Read-only
0xE0000FFC
Note
ITM registers are fully accessible in privileged mode. In user mode, all registers can be
read, but only the Stimulus Registers and Trace Enable Registers can be written, and
only when the corresponding Trace Privilege Register bit is set. Invalid user mode
writes to the ITM registers are discarded.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Table 11-19 ITM register summary (continued)
Reset value Description
See ITM Trace Control Register on
0x00000000
page 11-34
0x00000000 See ITM Integration Write Register on
page 11-35
See ITM Integration Read Register on
0x00000000
page 11-36
See ITM Integration Mode Control Register
0x00000000
on page 11-36
See ITM Lock Access Register on page 11-37
0x00000000
0x00000003 See ITM Lock Status Register on page 11-37
0x00000004 Value
Value
0x00000000
Value
0x00000000
Value
0x00000000
Value
0x00000001
Value
0x000000B0
0x0000002B Value
0x00000000 Value
Value
0x0000000D
Value
0x000000E0
Value
0x00000005
Value
0x000000B1
Non-Confidential
0x04
0x00
0x00
0x00
0x01
0xB0
0x2B
0x00
0x0D
0xE0
0x05
0xB1
System Debug
11-31