ARM Cortex-M3 Technical Reference Manual page 205

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9.2.3
Accessing the MPU using the alias registers
ARM DDI 0337G
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You can optimize the loading speed of the MPU registers using register aliasing. There
are three sets of Nested Vectored Interrupt Controller (NVIC) alias registers. These are
described in NVIC register descriptions on page 8-7.
The aliases access the registers in exactly the same way, and they exist to enable the use
of sequential writes (STM) to update between one and four regions. This is used when
disable/change/enable is not required.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Table 9-7 MPU protection region size field (continued)
Non-Confidential
Memory Protection Unit
Region
Size
b01110
32KB
b01111
64KB
b10000
128KB
b10001
256KB
b10010
512KB
b10011
1MB
b10100
2MB
b10101
4MB
b10110
8MB
b10111
16MB
b11000
32MB
b11001
64MB
b11010
128MB
b11011
256MB
b11100
512MB
b11101
1GB
b11110
2GB
b11111
4GB
9-11

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