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14.3.1
Periodic synchronization
14.3.2
Data and instruction address compare resources
ARM DDI 0337G
Unrestricted Access
Feature
Software access to registers
Readable registers
FIFO size
Minimum port size
Maximum port size
Normal port mode
Normal half-rate clocking/1:1
Demux port mode
Demux half-rate clocking/1:2
Mux port mode/2:1
1:4 port mode
Dynamic port mode (including stalling)
CPRT data
Load PC first
Fetch comparisons
Load data traced
The ETM uses a fixed synchronization packet generation frequency of every 1024 bytes
of trace.
The DWT provides four address comparators on the data bus that provide debug
functionality. Within the DWT unit, it is possible to specify the functions triggered by
a match, and one of these functions is to generate an ETM match input. These inputs are
presented to the ETM as Embedded In Circuit Emulator (ICE) comparator inputs.
A single DWT resource can trigger an ETM event and also generate instrumentation
trace directly from the same event.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Table 14-7 Cortex-M3 resources (continued)
Present on Cortex-M3 ETM
Yes
Yes
24 bytes
8 bits
8 bits
-
Yes - asynchronous
-
No
No
No
No. Supported by asynchronous port mode.
No
No
No
No
Non-Confidential
Embedded Trace Macrocell
14-9
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