ARM Cortex-M3 Technical Reference Manual page 76

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Table of Contents

System Control

Name of register

Application Interrupt/Reset Control Register

System Control Register

Configuration Control Register

System Handlers 4-7 Priority Register

System Handlers 8-11 Priority Register

System Handlers 12-15 Priority Register

System Handler Control and State Register

Configurable Fault Status Registers

Hard Fault Status Register

Debug Fault Status Register

Mem Manage Address Register

Bus Fault Address Register

Auxiliary Fault Status Register

PFR0: Processor Feature register0

PFR1: Processor Feature register1

DFR0: Debug Feature register0

AFR0: Auxiliary Feature register0

MMFR0: Memory Model Feature register0

MMFR1: Memory Model Feature register1

MMFR2: Memory Model Feature register2

MMFR3: Memory Model Feature register3

ISAR0: ISA Feature register0

ISAR1: ISA Feature register1

ISAR2: ISA Feature register2

ISAR3: ISA Feature register3

Non-Confidential

Table 3-1 NVIC registers (continued)

Unpredictable

Unpredictable

ARM DDI 0337G

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