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Microprocessor
Monitor debug-mode
MPU
Multi-layer
Nested Vectored Interrupt Controller (NVIC)
NVIC
Penalty
PFU
PMU
Power Management Unit (PMU)
Power-on reset
PPB
Prefetching
Prefetch Abort
Prefetch Unit (PFU)
ARM DDI 0337G
Unrestricted Access
See Processor.
One of two mutually exclusive debug modes. In Monitor debug-mode the processor
enables a software abort handler provided by the debug monitor or operating system
debug task. When a breakpoint or watchpoint is encountered, this enables vital system
interrupts to continue to be serviced while normal program execution is suspended.
See also Halt mode.
See Memory Protection Unit.
An interconnect scheme similar to a cross-bar switch. Each master on the interconnect
has a direct link to each slave, The link is not shared with other masters. This enables
each master to process transfers in parallel with other masters. Contention only occurs
in a multi-layer interconnect at a payload destination, typically the slave.
Provides the processor with configurable interrupt handling abilities.
See Nested Vectored Interrupt Controller.
The number of cycles in which no useful Execute stage pipeline activity can occur
because an instruction flow is different from that assumed or predicted.
See Prefetch Unit.
See Power Management Unit.
Provides the processor with power management capability.
See Cold reset.
See Private Peripheral Bus.
In pipelined processors, the process of fetching instructions from memory to fill up the
pipeline before the preceding instructions have finished executing. Prefetching an
instruction does not mean that the instruction has to be executed.
An indication from a memory system to the core that an instruction has been fetched
from an illegal memory location. An exception must be taken if the processor attempts
to execute the instruction. A Prefetch Abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction memory.
See also Data Abort, Abort.
The PFU fetches instructions from the memory system that can supply one word each
cycle. The PFU buffers up to three word fetches in its FIFO, which means that it can
buffer up to three 32-bit Thumb instructions or six 16-bit Thumb instructions.
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Glossary
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