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Introduction
1-6
•
Hardware divide.
•
Thumb and Debug states.
•
Handler and Thread modes.
•
Low latency ISR entry and exit.
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Processor state saving and restoration, with no instruction fetch overhead.
Exception vector is fetched from memory in parallel with the state saving,
enabling faster ISR entry.
—
Support for late arriving interrupts.
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Tightly coupled interface to interrupt controller enabling efficient
processing of late-arriving interrupts.
—
Tail-chaining of interrupts, enabling back-to-back interrupt processing
without the overhead of state saving and restoration between interrupts.
•
Interruptible-continued LDM/STM, PUSH/POP.
•
ARMv6 compatible BE8 and LE access support.
•
ARMv6 compatible unaligned access support.
Registers
The processor contains:
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13 general purpose 32-bit registers, R0 to R12
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Link Register (LR)
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Program Counter (PC)
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Program Status Register, xPSR
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two banked SP registers.
Memory interface
The processor has a Harvard interface to enable simultaneous instruction fetches with
data load/stores. Memory accesses are controlled by:
•
A separate Load Store Unit (LSU) that decouples load and store operations from
the Arithmetic and Logic Unit (ALU).
•
A 3-word entry Prefetch Unit (PFU). One word is fetched at a time. This can be
two Thumb instructions, one word-aligned Thumb 32-bit instruction, or the
upper/lower halfword of a halfword-aligned Thumb 32-bit instruction with one
Thumb instruction, or the lower/upper halfword of another halfword-aligned
Thumb 32-bit instruction. All fetch addresses from the core are word aligned. If
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