ARM Cortex-M3 Technical Reference Manual page 326

Embedded Trace Macrocell Interface
15-12
Execute cycle
9
10
11
12
13
14
15
Figure 15-9 on page 15-13 shows the timing sequence for the example opcode sequence
in Table 15-4 on page 15-11.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Table 15-4 Example of an opcode sequence (continued)
Fetch address
0x1046
0x1048
0x104A
0x104C
0x0FC4
0x0FC6
0x0FC8
Non-Confidential
Opcode
LDR NE r3,[r4,r2]
ADD r6,r3
NOP
BX r14
CMP
BEQ = Target2 // not taken
BX r5
ARM DDI 0337G
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