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Introduction
1.2.12
WIC
1.2.13
SW/SWJ-DP
1-10
The implementation options for the TPIU are:
•
If the ETM is present in your system, both of the input ports to the TPIU are
present. If the ETM is not present but the ITM is, then only one port is used,
saving the gate cost of one input FIFO.
•
You can replace the ARM TPIU block with a partner-specific CoreSight
compliant TPIU.
•
In a production device, the TPIU might have been removed.
Note
There is no Cortex-M3 trace capability if the TPIU is removed.
Chapter 17 Trace Port Interface Unit describes the TPIU.
You can configure the implementation to include a Wake-up Interrupt Controller
(WIC).
System power management on page 7-3 describes the WIC functionality.
You can configure the processor to have SW-DP or SWJ-DP debug port interfaces. The
debug port provides debug access to all registers and memory in the system, including
the processor registers.
The implementation options for the SW/SWJ-DP are:
•
Your implementation might contain either SW-DP or SWJ-DP.
•
You can replace the ARM SW-DP with a partner-specific CoreSight compliant
SW-DP.
•
You can replace the ARM SWJ-DP with a partner-specific CoreSight compliant
SWJ-DP.
•
You can include a partner-specific test interface in parallel with SW-DP or
SWJ-DP.
Note
The SW/SWJ-DP might not be present in the production device if no debug
functionality is present in the implementation.
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