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Bits
Field
[24]
-
[23]
ISRPREEMPT
[22]
ISRPENDING
[21:12]
VECTPENDING
[11]
RETTOBASE
[10]
-
[9]
-
[8:0]
VECTACTIVE
ARM DDI 0337G
Unrestricted Access
Table 8-15 Interrupt Control State Register bit assignments (continued)
Type
Function
-
Reserved
Read-only
You must only use this at debug time. It indicates that a pending interrupt
becomes active in the next running cycle. If C_MASKINTS is clear in the
Debug Halting Control and Status Register, the interrupt is serviced.
Read-only
Interrupt pending flag. Excludes NMI and Faults:
1 = interrupt pending
0 = interrupt not pending.
Read-only
Pending ISR number field. VECTPENDING contains the interrupt number
of the highest priority pending ISR.
Read-only
This bit is 1 when the set of all active exceptions minus the
IPSR_current_exception yields the empty set.
-
Reserved.
-
Reserved
Read-only
Active ISR number field. VECTACTIVE contains the interrupt number of
the currently running ISR, including NMI and Hard Fault. A shared handler
can use VECTACTIVE to determine which interrupt invoked it. You can
subtract 16 from the VECTACTIVE field to index into the Interrupt
Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority
Registers. INTISR[0] has vector number 16.
Reset clears the VECTACTIVE field.
Vector Table Offset Register
Use the Vector Table Offset Register to determine:
•
if the vector table is in RAM or code memory
•
the vector table offset.
The register address, access type, and Reset state are:
Address
0xE000ED08
Access
Read/write
Reset state
0x00000000
Figure 8-10 on page 8-22 shows the bit assignments of the Vector Table Offset Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
Nested Vectored Interrupt Controller
8-21
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