ARM Cortex-M3 Technical Reference Manual page 224

Core Debug
Bits Type
[17] Read/write
[16] Read/write
[15:11] -
[10] Read/write
[9] Read/write
[8] Read/write
[7] Read/write
[6] Read/write
[5] Read/write
[4] Read/write
[3:1] -
[0] Read/write
10-10
Table 10-4 Debug Exception and Monitor Control Register (continued)
Field Function
a Pend the monitor to activate when priority permits. This can wake up
MON_PEND
the monitor through the AHB-AP port. It is the equivalent to C_HALT
for Monitor debug.
This register does not reset on a system reset. It is only reset by a
power-on reset. Software in the reset handler or later, or by the DAP
must enable the debug monitor.
Enable the debug monitor. When enabled, the System handler priority
a
MON_EN
register controls its priority level. If disabled, then all debug events go
to Hard fault. C_DEBUGEN in the Debug Halting Control and Statue
register overrides this bit.
Vector catching is semi-synchronous. When a matching event is seen, a
Halt is requested. Because the processor can only halt on an instruction
boundary, it must wait until the next instruction boundary. As a result,
it stops on the first instruction of the exception handler. However, two
special cases exist when a vector catch has triggered:
•
•
- Reserved, SBZP
Debug trap on Hard Fault.
b
VC_HARDERR
b Debug Trap on interrupt/exception service errors. These are a subset of
VC_INTERR
other faults and catches before BUSERR or HARDERR.
b Debug Trap on normal Bus error.
VC_BUSERR
Debug trap on Usage Fault state errors.
b
VC_STATERR
b Debug trap on Usage Fault enabled checking errors.
VC_CHKERR
Debug trap on Usage Fault access to Coprocessor that is not present or
b
VC_NOCPERR
marked as not present in CAR register.
b Debug trap on Memory Management faults.
VC_MMERR
- Reserved, SBZP
b Reset Vector Catch. Halt running system if Core reset occurs.
VC_CORERESET
Copyright © 2005-2008 ARM Limited. All rights reserved.
If a fault is taken during vectoring, vector read or stack push
error, the halt occurs on the corresponding fault handler, for the
vector error or stack push.
If a late arriving interrupt comes in during vectoring, it is not
taken. That is, an implementation that supports the late arrival
optimization must suppress it in this case.
Non-Confidential
ARM DDI 0337G
Unrestricted Access