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Glossary
Warm reset
Watchpoint
WIC
Word
Word-invariant
Write buffer
Glossary-12
Also known as a core reset. Initializes the majority of the processor excluding the debug
controller and debug logic. This type of reset is useful if you are using the debugging
features of a processor.
A watchpoint is a mechanism provided by debuggers to halt program execution when
the data contained by a particular memory address is changed. Watchpoints are inserted
by the programmer to enable inspection of register contents, memory locations, and
variable values when memory is written to test that the program is operating correctly.
Watchpoints are removed after the program is successfully tested. See also Breakpoint.
See Wake-up Interrupt Controller.
A 32-bit data item.
In a word-invariant system, the address of each byte of memory changes when
switching between little-endian and big-endian operation, in such a way that the byte
with address A in one endianness has address A EOR 3 in the other endianness. As a
result, each aligned word of memory always consists of the same four bytes of memory
in the same order, regardless of endianness. The change of endianness occurs because
of the change to the byte addresses, not because the bytes are rearranged.
The ARM architecture supports word-invariant systems in ARMv3 and later versions.
When word-invariant support is selected, the behavior of load or store instructions that
are given unaligned addresses is instruction-specific, and is in general not the expected
behavior for an unaligned access. It is recommended that word-invariant systems use
the endianness that produces the required byte addresses at all times, apart possibly
from very early in their reset handlers before they have set up the endianness, and that
this early part of the reset handler must use only aligned word memory accesses.
See also Byte-invariant.
A pipeline stage for buffering write data to prevent bus stalls from stalling the processor.
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