ARM Cortex-M3 Technical Reference Manual page 360

Instruction Timing
18-6
• W = sleep wait
• B = barrier clearance.
In general, each instruction takes one cycle (one core clock) to start executing as
Table 18-1 on page 18-3 shows. Additional cycles can be taken because of fetch stalls.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
ARM DDI 0337G
Unrestricted Access