ARM Cortex-M3 Technical Reference Manual page 140

Clocking and Resets
6.3.4 SW-DP reset
6.3.5 Normal operation
6-8
The nTRST signal must be asserted with regard to the SWCLKTCK clock because the
SWJ-DP performs no synchronization.
SW-DP is reset with DBGRESETn. This reset must be synchronized to DBGCLK.
During normal operation, neither processor reset nor power-on reset is asserted. If the
SWJ-DP port is not being used, the value of nTRST does not matter.
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