ARM Cortex-M3 Technical Reference Manual page 156

Nested Vectored Interrupt Controller
Name of register
MMFR3: Memory Model Feature register3
ISAR0: ISA Feature register0
ISAR1: ISA Feature register1
ISAR2: ISA Feature register2
ISAR3: ISA Feature register3
ISAR4: ISA Feature register4
Software Trigger Interrupt Register
Peripheral identification register (PID4)
Peripheral identification register (PID5)
Peripheral identification register (PID6)
Peripheral identification register (PID7)
Peripheral identification register Bits 7:0 (PID0)
Peripheral identification register Bits 15:8
(PID1)
Peripheral identification register Bits 23:16
(PID2)
Peripheral identification register Bits 31:24
(PID3)
Component identification register Bits 7:0
(CID0)
Component identification register Bits 15:8
(CID1)
Component identification register Bits 23:16
(CID2)
Component identification register Bits 31:24
(CID3)
a. Reset value depends on the number of interrupts defined.
b. Bits [10:8] are reset. The ENDIANESS bit, bit [15], is set at reset by the sampling of BIGEND.
8-6
Type
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write Only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read Only
Read-only
Read-only
Read-only
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Table 8-1 NVIC registers (continued)
Reset
Address
value
0xE000ED5C 0x00000000
0xE000ED60 0x01141110
0xE000ED64 0x02111000
0xE000ED68 0x21112231
0xE000ED6C 0x01111110
0xE000ED70 0x01310102
-
0xE000EF00
0xE000EFD0 0x04
0xE000EFD4 0x00
0xE000EFD8 0x00
0xE000EFDC 0x00
0xE000EFE0 0x00
0xE000EFE4 0xB0
0xE000EFE8 0x2B
0xE000EFEC 0x00
0xE000EFF0 0x0D
0xE000EFF4 0xE0
0xE000EFF8 0x05
0xE000EFFC 0xB1
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ARM DDI 0337G
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