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Operation
Conditional branch
Clear bit field
Insert bit field from one register value into another
Bitwise AND register value with complement of immediate
12-bit value
Bitwise AND register value with complement of shifted
register value
Branch with link
Branch with link (immediate)
Unconditional branch
Clear exclusive clears the local record of the executing
processor that an address has had a request for an exclusive
access.
Return number of leading zeros in register value
Compare register value with two's complement of immediate
12-bit value
Compare register value with two's complement of shifted
register value
Compare register value with immediate 12-bit value
Compare register value with shifted register value
Data memory barrier
Data synchronization barrier
Exclusive OR register value with immediate 12-bit value
Exclusive OR register value with shifted register value
Instruction synchronization barrier
Load multiple memory registers, increment after or decrement
before
ARM DDI 0337G
Unrestricted Access
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
Assembler
B{cond}.W <label>
BFC.W <Rd>, #<lsb>, #<width>
BFI.W <Rd>, <Rn>, #<lsb>, #<width>
BIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
BIC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
BL <label>
BL<c> <label>
B.W <label>
CLREX <c>
CLZ.W <Rd>, <Rn>
CMN.W <Rn>, #<modify_constant(immed_12)>
CMN.W <Rn>, <Rm>{, <shift>}
CMP.W <Rn>, #<modify_constant(immed_12)>
CMP.W <Rn>, <Rm>{, <shift>}
DMB <c>
DSB <c>
EOR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
EOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
ISB <c>
LDM{IA|DB}.W <Rn>{!}, <registers>
Programmer's Model
2-17
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