ARM Cortex-M3 Technical Reference Manual page 409

R2p0
Hide thumbs Also See for Cortex-M3:
Table of Contents

Advertisement

SWJ-DP
Synchronization primitive
System memory
TAP
Test Access Port (TAP)
Thread Control
Block
Thumb instruction
Thumb state
TPA
TPIU
Trace Port Interface Unit (TPIU)
Unaligned
UNP
Unpredictable
Wake-up Interrupt
Controller (WIC)
ARM DDI 0337G
Unrestricted Access
See Serial-Wire JTAG Debug Port.
The memory synchronization primitive instructions are those instructions that are used
to ensure memory synchronization. That is, the LDREX and STREX instructions.
Memory space at
0x20000000
.
0xE00FFFFF
See Test access port.
The collection of four mandatory and one optional terminals that form the input/output
and control interface to a JTAG boundary-scan architecture. The mandatory terminals
are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is
mandatory in ARM cores because it is used to reset the debug logic.
A data structure used by an operating system kernel to maintain information specific to
a single thread of execution.
A halfword that specifies an operation for an ARM processor in Thumb state to
perform. Thumb instructions must be halfword-aligned.
A processor that is executing Thumb (16-bit) halfword aligned instructions is operating
in Thumb state.
See Trace Port Analyzer.
See Trace Port Interface Unit.
Drains trace data and acts as a bridge between the on-chip trace data and the data stream
captured by a TPA.
A data item stored at an address that is not divisible by the number of bytes that defines
the data size is said to be unaligned. For example, a word stored at an address that is not
divisible by four.
See Unpredictable.
For reads, the data returned when reading from this location is unpredictable. It can have
any value. For writes, writing to this location causes unpredictable behavior, or an
unpredictable change in device configuration. Unpredictable instructions must not halt
or hang the processor, or any part of the system.
The Wake-up Interrupt Controller provides significantly reduced gate count interrupt
detection and prioritization logic.
Copyright © 2005-2008 ARM Limited. All rights reserved.
to
, excluding PPB space at
0xFFFFFFFF
Non-Confidential
Glossary
to
0xE0000000
Glossary-11

Advertisement

Table of Contents
loading

Table of Contents