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1.2.2
NVIC
1.2.3
Bus matrix
ARM DDI 0337G
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a Thumb 32-bit instruction is halfword aligned, two fetches are necessary to fetch
the Thumb 32-bit instruction. However, the 3-entry prefetch buffer ensures that a
stall cycle is only necessary for the first halfword Thumb 32-bit instruction
fetched.
The NVIC is tightly coupled to the processor core. This facilitates low latency exception
processing. The main features include:
•
a configurable number of external interrupts, from 1 to 240
•
a configurable number of bits of priority, from three to eight bits
•
level and pulse interrupt support
•
dynamic reprioritization of interrupts
•
priority grouping
•
support for tail-chaining of interrupts
•
processor state automatically saved on interrupt entry, and restored on interrupt
exit, with no instruction overhead.
Chapter 8 Nested Vectored Interrupt Controller describes the NVIC in detail.
The bus matrix connects the processor and debug interface to the external buses. The
bus matrix interfaces to the following external buses:
•
ICode bus. This is for instruction and vector fetches from code space. This is a
32-bit AHB-Lite bus.
•
DCode bus. This is for data load/stores and debug accesses to code space. This is
a 32-bit AHB-Lite bus.
•
System bus. This is for instruction and vector fetches, data load/stores and debug
accesses to system space. This is a 32-bit AHB-Lite bus.
•
PPB. This is for data load/stores and debug accesses to PPB space. This is a 32-bit
APB (v3.0) bus.
The bus matrix also controls the following:
•
Unaligned accesses. The bus matrix converts unaligned processor accesses into
aligned accesses.
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Introduction
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