ARM Cortex-M3 Technical Reference Manual page 16

List of Figures
Figure 7-3
Figure 7-4
Figure 7-5
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 8-14
Figure 8-15
Figure 8-16
Figure 8-17
Figure 8-18
Figure 8-19
Figure 8-20
Figure 8-21
Figure 8-22
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 10-1
Figure 10-2
Figure 10-3
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure 11-6
Figure 11-7
Figure 11-8
Figure 11-9
Figure 11-10
Figure 11-11
Figure 11-12
Figure 11-13
Figure 11-14
xvi
WIC mode enable sequence .................................................................................... 7-7
Power down timing sequence ................................................................................... 7-8
PMU, WIC, and Cortex-M3 interconnect .................................................................. 7-9
Interrupt Controller Type Register bit assignments .................................................. 8-7
Auxiliary Control Register bit assignments ............................................................... 8-8
SysTick Control and Status Register bit assignments .............................................. 8-9
SysTick Reload Value Register bit assignments .................................................... 8-11
SysTick Current Value Register bit assignments .................................................... 8-11
SysTick Calibration Value Register bit assignments .............................................. 8-12
Interrupt Priority Registers 0-31 bit assignments .................................................... 8-17
CPUID Base Register bit assignments ................................................................... 8-18
Interrupt Control State Register bit assignments .................................................... 8-20
Vector Table Offset Register bit assignments ........................................................ 8-22
Application Interrupt and Reset Control Register bit assignments ......................... 8-23
System Control Register bit assignments ............................................................... 8-25
Configuration Control Register bit assignments ..................................................... 8-27
System Handler Priority Registers bit assignments ................................................ 8-29
System Handler Control and State Register bit assignments ................................. 8-30
Configurable Fault Status Registers bit assignments ............................................. 8-32
Memory Manage Fault Status Register bit assignments ........................................ 8-33
Bus Fault Status Register bit assignments ............................................................. 8-34
Usage Fault Status Register bit assignments ......................................................... 8-36
Hard Fault Status Register bit assignments ........................................................... 8-37
Debug Fault Status Register bit assignments ......................................................... 8-39
Software Trigger Interrupt Register bit assignments .............................................. 8-42
MPU Type Register bit assignments ........................................................................ 9-4
MPU Control Register bit assignments ..................................................................... 9-5
MPU Region Number Register bit assignments ....................................................... 9-7
MPU Region Base Address Register bit assignments .............................................. 9-8
MPU Region Attribute and Size Register bit assignments ........................................ 9-9
Debug Halting Control and Status Register bit assignments .................................. 10-4
Debug Core Register Selector Register bit assignments ....................................... 10-6
Debug Exception and Monitor Control Register bit assignments ........................... 10-9
System debug access block diagram ..................................................................... 11-4
Flash Patch Control Register bit assignments ........................................................ 11-8
Flash Patch Remap Register bit assignments ...................................................... 11-10
Flash Patch Comparator Registers bit assignments ............................................. 11-11
DWT Control Register bit assignments ................................................................. 11-16
DWT CPI Count Register bit assignments ............................................................ 11-20
DWT Exception Overhead Count Register bit assignments ................................. 11-21
DWT Sleep Count Register bit assignments ........................................................ 11-21
DWT LSU Count Register bit assignments ........................................................... 11-22
DWT Fold Count Register bit assignments ........................................................... 11-23
DWT Mask Registers 0-3 bit assignments ............................................................ 11-25
DWT Function Registers 0-3 bit assignments ...................................................... 11-26
ITM Trace Privilege Register bit assignments ...................................................... 11-33
ITM Trace Control Register bit assignments ........................................................ 11-34
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