ARM Cortex-M3 Technical Reference Manual page 403

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Byte-invariant
Clock gating
Clocks Per Instruction (CPI)
Cold reset
Context
Core
Core reset
CoreSight
CPI
Cycles Per instruction (CPI)
Data Abort
DCode Memory
ARM DDI 0337G
Unrestricted Access
In a byte-invariant system, the address of each byte of memory remains unchanged
when switching between little-endian and big-endian operation. When a data item
larger than a byte is loaded from or stored to memory, the bytes making up that data item
are arranged into the correct order depending on the endianness of the memory access.
The ARM architecture supports byte-invariant systems in ARMv6 and later versions.
When byte-invariant support is selected, unaligned halfword and word memory
accesses are also supported. Multi-word accesses are expected to be word-aligned.
See also Word-invariant.
Gating a clock signal for a macrocell with a control signal and using the modified clock
that results to control the operating state of the macrocell.
See Cycles Per Instruction (CPI).
Also known as power-on reset.
See also Warm reset.
The environment that each process operates in for a multitasking operating system.
See also Fast context switch.
A core is that part of a processor that contains the ALU, the datapath, the
general-purpose registers, the Program Counter, and the instruction decode and control
circuitry.
See Warm reset.
The infrastructure for monitoring, tracing, and debugging a complete system on chip.
See Cycles per instruction.
Cycles per instruction (or clocks per instruction) is a measure of the number of
computer instructions that can be performed in one clock cycle. This figure of merit can
be used to compare the performance of different CPUs that implement the same
instruction set against each other. The lower the value, the better the performance.
An indication from a memory system to the core of an attempt to access an illegal data
memory location. An exception must be taken if the processor attempts to use the data
that caused the abort.
See also Abort.
Memory space at
0x00000000
Copyright © 2005-2008 ARM Limited. All rights reserved.
to
0x1FFFFFFFF
.
Non-Confidential
Glossary
Glossary-5

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