ARM Cortex-M3 Technical Reference Manual page 246

R2p0
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System Debug
Bits
Field
[12]
PCSAMPLEENA
[11:10]
SYNCTAP
[9]
CYCTAP
[8:5]
POSTCNT
[4:1]
POSTPRESET
[0]
CYCCNTENA
11-18
Table 11-7 DWT Control Register bit assignments (continued)
Function
Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter
triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this
bit overrides CYCEVTENA (bit [20]).
1 = PC Sampling event enabled.
0 = PC Sampling event disabled.
Reset clears the PCSAMPLENA bit.
Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here
picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT
register. To use synchronization (heartbeat and hot-connect synchronization),
CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and
SYNCENA must be set to 1.
0b00 = Disabled. No synch counting.
0b01 = Tap at CYCCNT bit 24.
0b10 = Tap at CYCCNT bit 26.
0b11 = Tap at CYCCNT bit 28.
Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]:
CYCTAP = 0 selects bit [6] to tap
CYCTAP = 1 selects bit [10] to tap.
When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into
the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit
change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.
Post-scalar counter for CYCTAP.
When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is
down-counted when not 0.
If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the
value from POSTPRESET (bits [4:1]).
Reload value for POSTCNT, bits [8:5], post-scalar counter.
If this value is 0, events are triggered on each tap change (a power of 2, such as 1<<6 or
1<<10).
If this field has a non-0 value, this forms a count-down value, to be reloaded into
POSTCNT each time it reaches 0. For example, a value 1 in this register means an event
is formed every other tap change.
Enable the CYCCNT counter. If not enabled, the counter does not count and no event is
generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize
the CYCCNT counter to 0.
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