ARM Cortex-M3 Technical Reference Manual page 125

Fault
Imprecise data bus error
No Coprocessor
Undefined Instruction
Attempt to execute an
instruction when in an
invalid ISA state. For
example, not Thumb
Return to
PC=EXC_RETURN
when not enabled or with
invalid magic number
Illegal unaligned load or
store
Divide By 0
SVC
ARM DDI 0337G
Unrestricted Access
Bit name Handler
IMPRECISERR BusFault
NOCP UsageFault
UNDEFINSTR UsageFault
INVSTATE UsageFault
INVPC UsageFault
UNALIGNED UsageFault
DIVBYZERO UsageFault
- SVCall
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Table 5-10 Faults (continued)
Notes
Late bus error because of data
access. Exact instruction is no
longer known. This is pended and
not synchronous. It does not cause
FORCED.
Truly does not exist, or not present
bit.
Unknown instruction.
Attempt to execute in an invalid
EPSR state. For example, after a
BX type instruction has changed
state. This includes states after
return from exception including
inter-working states.
Illegal exit, caused either by an
illegal EXC_RETURN value, an
EXC_RETURN and stacked EPSR
value mismatch, or an exit while
the current EPSR is not contained
in the list of currently active
exceptions.
This occurs when any load-store
multiple instruction attempts to
access a non-word aligned
location. It can be enabled to occur
for any load-store that is unaligned
to its size using the
UNALIGN_TRP bit.
This can be enabled to occur when
SDIV or UDIV is executed with a
divisor of 0, and the DIV_0_TRP
bit is set.
System request (Service Call).
Exceptions
Trap enable bit
BUSERR
NOCPERR
STATERR
STATERR
STATERR
CHKERR
CHKERR
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5-29