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Glossary
JTAG
JTAG Debug Port (JTAG-DP)
JTAG-DP
LE
Little-endian
Little-endian memory
Load/store architecture
Load Store Unit (LSU)
LSU
Macrocell
Memory coherency
Memory Protection Unit (MPU)
Glossary-8
See Joint Test Action Group.
An optional external interface for the DAP that provides a standard JTAG interface for
debug access.
See JTAG Debug Port.
Little endian view of memory in both byte-invariant and word-invariant systems. See
also Byte-invariant, Word-invariant.
Byte ordering scheme in which bytes of increasing significance in a data word are stored
at increasing addresses in memory.
See also Big-endian and Endianness.
Memory in which:
•
a byte or halfword at a word-aligned address is the least significant byte or
halfword within the word at that address
•
a byte at a halfword-aligned address is the least significant byte within the
halfword at that address.
See also Big-endian memory.
A processor architecture where data-processing operations only operate on register
contents, not directly on memory contents.
The part of a processor that handles load and store transfers.
See Load Store Unit.
A complex logic block with a defined interface and behavior. A typical VLSI system
comprises several macrocells (such as a processor, an ETM, and a memory block) plus
application-specific logic.
A memory is coherent if the value read by a data read or instruction fetch is the value
that was most recently written to that location. Memory coherency is made difficult
when there are multiple possible physical locations that are involved, such as a system
that has main memory, a write buffer and a cache.
Hardware that controls access permissions to blocks of memory. Unlike an MMU, an
MPU does not modify addresses.
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