ARM Cortex-M3 Technical Reference Manual page 15

List of Figures
Cortex-M3 Technical Reference Manual
Figure 1-1
Figure 1-2
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 4-1
Figure 4-2
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 6-1
Figure 6-2
Figure 6-3
Figure 7-1
Figure 7-2
ARM DDI 0337G
Unrestricted Access
Key to timing diagram conventions .......................................................................... xxiii
Cortex-M3 block diagram .......................................................................................... 1-5
Cortex-M3 pipeline stages ...................................................................................... 1-12
Processor register set ............................................................................................... 2-4
Application Program Status Register bit assignments .............................................. 2-6
Interrupt Program Status Register bit assignments .................................................. 2-6
Execution Program Status Register .......................................................................... 2-8
Little-endian and big-endian memory formats ......................................................... 2-12
Processor memory map ............................................................................................ 4-2
Bit-band mapping ...................................................................................................... 4-6
Stack contents after pre-emption ............................................................................ 5-11
Exception entry timing ............................................................................................. 5-13
Tail-chaining timing ................................................................................................. 5-14
Late-arriving exception timing ................................................................................. 5-15
Exception exit timing ............................................................................................... 5-18
Interrupt handling flowchart ..................................................................................... 5-34
Pre-emption flowchart ............................................................................................. 5-35
Return from interrupt flowchart ................................................................................ 5-36
Reset signals ............................................................................................................. 6-6
Power-on reset .......................................................................................................... 6-6
Internal reset synchronization ................................................................................... 6-7
SLEEPING power control example ........................................................................... 7-4
SLEEPDEEP power control example ........................................................................ 7-5
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
xv