ARM Cortex-M3 Technical Reference Manual page 396

R2p0
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Revisions
Change
More information added about the stacked xPSR
Reset value of Configuration Control Register changed to
0x00000200
System and Vendor_SYS memory regions added to table of
memory region permissions
Memory region for Private Peripheral Bus changed to +0000000
SLEEPHOLDREQ changed to SLEEPHOLDREQn
SLEEPHOLDACK changed to SLEEPHOLDACKn
DEEPSLEEP signal changed to SLEEPDEEP
DBGRESTARTACK changed to DBGRESTARTED
DBGRESTARTREQ changed to DBGRESTART
New subsection added to describe the WIC
Address of Irq 224 to 239 Priority Register changed to
Enhanced description of function of C_MASKINTS field
Settings for DWT Function Registers updated
Minor change to timing information of ETMIA
Change to timing information for ETMIVALID
SLEEPHOLDREQn removed from table of miscellaneous input
ports timing parameters
Table of low power input ports timing parameters added
FIXHMASTERTYPE added to table of debug input ports timing
parameters
Input changed to Output in table header
SLEEPING, SLEEPDEEP, and SLEEPHOLDACKn removed
from table of miscellaneous output ports timing parameters
B-6
Table B-2 Differences between issue F and issue G (continued)
0xE000E4EC
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
Location
Saved xPSR bits on page 2-9
Table 3-1 on page 3-2
Table 4-2 on page 4-4
Throughout the book
Throughout the book
Throughout the book
Throughout the book
Throughout the book
Using the Wake-up Interrupt Controller on page 7-6
Table 8-1 on page 8-3
Table 10-2 on page 10-4
Table 11-18 on page 11-28
Figure 15-4 on page 15-9
Figure 15-7 on page 15-11
Table 19-1 on page 19-2
Table 19-2 on page 19-2
Table 19-6 on page 19-4
Table 19-9 on page 19-5, Table 19-11 on page 19-6
and Table 19-12 on page 19-8 to Table 19-16 on
page 19-10 inclusive
Miscellaneous output ports timing parameters on
page 19-5
ARM DDI 0337G
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