ARM Cortex-M3 Technical Reference Manual page 10

List of Tables
Table 5-5
Table 5-6
Table 5-7
Table 5-8
Table 5-9
Table 5-10
Table 5-11
Table 5-12
Table 5-13
Table 5-14
Table 5-15
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 7-1
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 8-9
Table 8-10
Table 8-11
Table 8-12
Table 8-13
Table 8-14
Table 8-15
Table 8-16
Table 8-17
Table 8-18
Table 8-19
Table 8-20
Table 8-21
Table 8-22
Table 8-23
Table 8-24
Table 8-25
Table 8-26
Table 8-27
Table 8-28
Table 8-29
Table 8-30
Table 9-1
x
Exception exit steps ................................................................................................ 5-17
Exception return behavior ....................................................................................... 5-19
Reset actions .......................................................................................................... 5-20
Reset boot-up behavior .......................................................................................... 5-21
Transferring to exception processing ...................................................................... 5-24
Faults ...................................................................................................................... 5-28
Debug faults ............................................................................................................ 5-30
Fault status and fault address registers .................................................................. 5-31
Privilege and stack of different activation levels ..................................................... 5-32
Exception transitions ............................................................................................... 5-32
Exception subtype transitions ................................................................................. 5-33
Cortex-M3 processor clocks ..................................................................................... 6-2
Cortex-M3 macrocell clocks ...................................................................................... 6-2
Reset inputs .............................................................................................................. 6-4
Reset modes ............................................................................................................. 6-5
Supported sleep modes ............................................................................................ 7-3
NVIC registers .......................................................................................................... 8-3
Interrupt Controller Type Register bit assignments .................................................. 8-8
Auxiliary Control Register bit assignments ............................................................... 8-9
SysTick Control and Status Register bit assignments ............................................ 8-10
SysTick Reload Value Register bit assignments .................................................... 8-11
SysTick Current Value Register bit assignments .................................................... 8-12
SysTick Calibration Value Register bit assignments .............................................. 8-12
Interrupt Set-Enable Register bit assignments ....................................................... 8-14
Interrupt Clear-Enable Register bit assignments .................................................... 8-14
Interrupt Set-Pending Register bit assignments ..................................................... 8-15
Interrupt Clear-Pending Registers bit assignments ................................................ 8-16
Active Bit Register bit assignments ........................................................................ 8-16
Interrupt Priority Registers 0-31 bit assignments .................................................... 8-18
CPUID Base Register bit assignments ................................................................... 8-18
Interrupt Control State Register bit assignments .................................................... 8-20
Vector Table Offset Register bit assignments ........................................................ 8-22
Application Interrupt and Reset Control Register bit assignments ......................... 8-23
System Control Register bit assignments ............................................................... 8-26
Configuration Control Register bit assignments ..................................................... 8-27
System Handler Priority Registers bit assignments ................................................ 8-29
System Handler Control and State Register bit assignments ................................. 8-30
Memory Manage Fault Status Register bit assignments ........................................ 8-33
Bus Fault Status Register bit assignments ............................................................. 8-35
Usage Fault Status Register bit assignments ......................................................... 8-36
Hard Fault Status Register bit assignments ........................................................... 8-38
Debug Fault Status Register bit assignments ......................................................... 8-39
Memory Manage Fault Address Register bit assignments ..................................... 8-40
Bus Fault Address Register bit assignments .......................................................... 8-41
Auxiliary Fault Status Register bit assignments ...................................................... 8-42
Software Trigger Interrupt Register bit assignments .............................................. 8-42
MPU registers ........................................................................................................... 9-3
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