ARM Cortex-M3 Technical Reference Manual page 9

List of Tables
Cortex-M3 Technical Reference Manual
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 4-1
Table 4-2
Table 4-3
Table 5-1
Table 5-2
Table 5-3
Table 5-4
ARM DDI 0337G
Unrestricted Access
Change History ............................................................................................................. ii
Application Program Status Register bit assignments .............................................. 2-6
Interrupt Program Status Register bit assignments .................................................. 2-7
Bit functions of the EPSR .......................................................................................... 2-8
16-bit Cortex-M3 instruction summary .................................................................... 2-13
32-bit Cortex-M3 instruction summary .................................................................... 2-16
NVIC registers ........................................................................................................... 3-2
Core debug registers ................................................................................................. 3-5
Flash patch register summary ................................................................................... 3-6
DWT register summary ............................................................................................. 3-7
ITM register summary ............................................................................................... 3-9
AHB-AP register summary ...................................................................................... 3-10
Summary of Debug interface port registers ............................................................ 3-10
MPU registers ......................................................................................................... 3-11
TPIU registers ......................................................................................................... 3-12
ETM registers .......................................................................................................... 3-13
Memory interfaces ..................................................................................................... 4-3
Memory region permissions ...................................................................................... 4-4
ROM table ................................................................................................................. 4-7
Exception types ......................................................................................................... 5-4
Priority-based actions of exceptions ......................................................................... 5-6
Priority grouping ........................................................................................................ 5-8
Exception entry steps .............................................................................................. 5-12
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
ix