ARM Cortex-M3 Technical Reference Manual page 154

Nested Vectored Interrupt Controller
Name of register
Irq 0 to 31 Clear Enable Register
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Irq 224 to 239 Clear Enable Register
Irq 0 to 31 Set Pending Register
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Irq 224 to 239 Set Pending Register
Irq 0 to 31 Clear Pending Register
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Irq 224 to 239 Clear Pending Register
Irq 0 to 31 Active Bit Register
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Irq 224 to 239 Active Bit Register
Irq 0 to 3 Priority Register
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8-4
Type
Read/write
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Read/write
Read/write
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Read/write
Read/write
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Read/write
Read-only
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Read-only
Read/write
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Non-Confidential
Table 8-1 NVIC registers (continued)
Reset
Address
value
0xE000E180 0x00000000
. .
. .
. .
0xE000E19C 0x00000000
0xE000E200 0x00000000
. .
. .
. .
0xE000E21C 0x00000000
0xE000E280 0x00000000
. .
. .
. .
0xE000E29C 0x00000000
0xE000E300 0x00000000
. .
. .
. .
0xE000E31C 0x00000000
0xE000E400 0x00000000
. .
. .
. .
Page
page 8-14
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page 8-14
page 8-15
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page 8-15
page 8-15
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page 8-15
page 8-16
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page 8-16
page 8-17
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ARM DDI 0337G
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