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ARM DDI 0337G
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Table 8-14 CPUID Base Register bit assignments (continued)
Bits
Field
[19:16]
Constant
[15:4]
PARTNO
[3:0]
REVISION
Interrupt Control State Register
Use the Interrupt Control State Register to:
•
set a pending Non-Maskable Interrupt (NMI)
•
set or clear a pending SVC
•
set or clear a pending SysTick
•
check for pending exceptions
•
check the vector number of the highest priority pended exception
•
check the vector number of the active exception.
The register address, access type, and Reset state are:
Address
0xE000ED04
Access
Read/write or read-only
Reset state
0x00000000
Figure 8-9 on page 8-20 shows the bit assignments of the Interrupt Control State
Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Function
Reads as
0xF
Number of processor within family:
[11:10] b11 = Cortex family
[9:8] b00 = version
[7:6] b00 = reserved
[5:4] b10 = M (v7-M)
[3:0] X = family member. Cortex-M3 family is b0011.
Implementation defined revision number.
Non-Confidential
Nested Vectored Interrupt Controller
8-19
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