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ARM DDI 0337G
Unrestricted Access
TraceEnable Control 1 Register
The TraceEnable Control 1 Register is one of the registers that configures TraceEnable.
Only bit [25], Trace start/stop enable, is implemented as follows:
•
0 - Tracing is unaffected by the trace start/stop logic.
•
1 - Tracing is controlled by the trace on and off addresses configured for the trace
start/stop logic.
The trace start/stop resource (resource
ETM ID Register
The ETM ID Register holds the ETM architecture variant, and precisely defines the
programmer's model for the ETM.
Reset value:
0x4114F242
This indicates:
•
ARM implementor
•
special branch encoding, affects bits [7:6] of each byte
•
32-bit Thumb instruction supported
•
core family is found elsewhere
•
ETMv3.4
•
implementation revision 2.
Configuration Code Extension Register
The Configuration Code Extension Register holds additional bits for ETM
configuration code. It describes the extended external inputs.
Reset value:
0x00018800
This register indicates:
•
start/stop block uses embedded In Circuit Emulator (ICE) inputs
•
four embedded ICE inputs
•
no data comparisons supported
•
all registers are readable
•
no extended external input supported.
Copyright © 2005-2008 ARM Limited. All rights reserved.
) is unaffected by the value of this bit.
0x5F
Non-Confidential
Embedded Trace Macrocell
14-21
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