Table of Contents
Advertisement
Bus Interface
12.5.5
Memory attributes
12.5.6
Pipelined instruction fetches
12-8
The processor exports memory attributes on the System bus by using a sideband bus
called MEMATTRS. For more information, see Memory attributes on page 12-15.
To provide a clean timing interface on the System bus, instruction and vector fetch
requests to this bus are registered. This results in an additional cycle of latency because
instructions fetched from the System bus take two cycles. This also means that
back-to-back instruction fetches from the System bus are not possible.
Note
Instruction fetch requests to the ICode bus are not registered. Performance critical code
must run from the ICode interface.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
ARM DDI 0337G
Unrestricted Access
Advertisement
Table of Contents
