ARM Cortex-M3 Technical Reference Manual page 68

Programmer's Model
Operation
Memory signed halfword [15:0] from base register address
immediate 8-bit offset, preindexed
Memory signed halfword [15:0] from register address shifted
left by 0, 1, 2, or 3 places
Memory signed halfword from PC address immediate 12-bit
offset
Logical shift left register value by number in register
Logical shift right register value by number in register
Multiply two signed or unsigned register values and add the
low 32 bits to a register value
Multiply two signed or unsigned register values and subtract
the low 32 bits from a register value
Move immediate 12-bit value to register
Move shifted register value to register
Move immediate 16-bit value to top halfword [31:16] of
register
Move immediate 16-bit value to bottom halfword [15:0] of
register and clear top halfword [31:16]
Move to register from status
Move to status register
Multiply two signed or unsigned register values
No operation
Logical OR NOT register value with immediate 12-bit value
Logical OR NOT register value with shifted register value
Logical OR register value with immediate 12-bit value
Logical OR register value with shifted register value
Reverse bit order
Reverse bytes in word
2-20
Table 2-5 32-bit Cortex-M3 instruction summary (continued)
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Assembler
LDRSH.W <Rxf>, [<Rn>, #<+/–<offset_8>]
LDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
LDRSH.W <Rxf>, [PC, #+/–<offset_12>]
LSL{S}.W <Rd>, <Rn>, <Rm>
LSR{S}.W <Rd>, <Rn>, <Rm>
MLA.W <Rd>, <Rn>, <Rm>, <Racc>
MLS.W <Rd>, <Rn>, <Rm>, <Racc>
MOV{S}.W <Rd>, #<modify_constant(immed_12)>
MOV{S}.W <Rd>, <Rm>{, <shift>}
MOVT.W <Rd>, #<immed_16>
MOVW.W <Rd>, #<immed_16>
MRS<c> <Rd>, <psr>
MSR<c> <psr>_<fields>,<Rn>
MUL.W <Rd>, <Rn>, <Rm>
NOP.W
ORN{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
ORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}
ORR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
ORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
RBIT.W <Rd>, <Rm>
REV.W <Rd>, <Rm>
!
ARM DDI 0337G
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