ARM Cortex-M3 Technical Reference Manual page 392

R2p0
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Revisions
Change
Configurable options information expanded to include:
Added DWT configurability information
New subsections for ITM, AHB-AP, FPB and
Observation
New subsection added to list changes in functionality
between r1p1 and r2p0
Information about the programmer's model updated
Definition of ICI field of Execution Program Status Register
updated
Table of nonsupported Thumb instructions removed.
Second footnote on Table 5-1 removed.
Addition of note to vector table and reset description
Description of SLEEPING and SLEEPDEEP signals
updated.
Description of extending sleep functionality added
Addition of Auxiliary Control Register
Irq 0 to 31 Priority Register amended to Irq 0 to 3 Priority
Register
Irq 236 to 239 Priority Register amended to Irq 224 to 239
Priority Register
HCLK changed to FCLK
Addition of ascending MPU region priority information
Extra paragraph added.
Debug Core Register Selector Register REGSEL bit field
function updated
Extra paragraph added.
Paragraph added about removing FPB
B-2
Table B-1 Differences between issue E and issue F (continued)
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
Location
Differences in functionality between r1p1 and r2p0 on
page 1-20
About the programmer's model on page 2-2
Table 2-3 on page 2-8
Table 5-1 on page 5-4
Vector Table and Reset on page 5-20
System power management on page 7-3
Extending sleep on page 7-5
Table 8-1 on page 8-3 and NVIC register descriptions on
page 8-7
Table 8-1 on page 8-3
Table 8-1 on page 8-3
Level versus pulse interrupts on page 8-43
About the MPU on page 9-2
About core debug on page 10-2
Table 10-3 on page 10-7
About system debug on page 11-2
FPB on page 11-6
ARM DDI 0337G
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