Table of Contents
Advertisement
5.3.1
Priority levels
5.3.2
Priority grouping
ARM DDI 0337G
Unrestricted Access
The NVIC supports software-assigned priority levels. You can assign a priority level
from 0 to 255 to an interrupt by writing to the eight-bit PRI_N field in an Interrupt
Priority Register, see Interrupt Priority Registers on page 8-17. Hardware priority
decreases with increasing interrupt number. Priority level 0 is the highest priority level,
and priority level 255 is the lowest. The priority level overrides the hardware priority.
For example, if you assign priority level 1 to IRQ[0] and priority level 0 to IRQ[31],
then IRQ[31] has higher priority than IRQ[0].
Note
Software prioritization does not affect reset, Non-Maskable Interrupt (NMI), and hard
fault. They always have higher priority than the external interrupts.
When multiple interrupts have the same priority number, the pending interrupt with the
lowest interrupt number takes precedence. For example, if both IRQ[0] and IRQ[1] are
priority level 1, then IRQ[0] has higher priority than IRQ[1].
For more information on the PRI_N fields, see Interrupt Priority Registers on
page 8-17.
To increase priority control in systems with large numbers of interrupts, the NVIC
supports priority grouping. You can use the PRIGROUP field in the Application
Interrupt and Reset Control Register on page 8-22 to split the value in every PRI_N
field into a pre-emption priority field and a subpriority field. The pre-emption priority
group is referred to as the group priority. Where multiple pending exceptions share the
same group priority, the sub-priority bit field resolves the priority within a group. This
is referred to as the sub-priority within the group. The combination of the group priority
and the sub-priority is referred to generally as the priority. Where two pending
exceptions have the same priority, the lower pending exception number has priority over
the higher pending exception number. This is consistent with the priority precedence
scheme.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
Exceptions
5-7
Advertisement
Table of Contents
