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Instruction Timing
Instruction type
Size
Shift operations
32
Miscellaneous
32
Table Branch
16
Multiply
32
Multiply with
32
64-bit result
Load-store
32
addressing
Load-store Single
32
Load-store
32
Multiple
Load-store Special
32
Branches
32
System
32
System
16
Extended32
32
18-4
Cycles count
1
1
a
4+P
1 or 2
c
3-7
-
b
a
2
(+P
if PC is destination)
b
a
1+N
(+P
if PC is loaded)
b
1+N
a
1+P
1-2
1-2
1
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Table 18-1 Instruction timings (continued)
Description
ASR{S}, LSL{S}, LSR{S}, ROR{S}, and RRX{S}.
REV, REV16, REVSH, RBIT, CLZ, SXTB, SXTH,
UXTB, and UXTH. Extension instructions same as
corresponding ARM v6 16-bit instructions.
Table branches for switch/case use. These are LDR with
shifts and then branch.
MUL, MLA, and MLS. MUL is one cycle and MLA and
MLS are two cycles.
UMULL, SMULL, UMLAL, and SMLAL. Cycle count
based on input sizes. That is, ABS(inputs) < 64K
terminates early.
Supports Format PC+/-imm12, Rbase+imm12,
Rbase+/-imm8, and adjusted register including shifts. T
variants used when in Privilege mode.
LDR, LDRB, LDRSB, LDRH, LDRSH, STR, STRB, and
STRH, and T variants. PLD and PLI are both hints and so
act as a NOP.
STM, LDM, LDRD, and STRD.
LDREX, STREX, LDREXB, LDREXH, STREXB,
STREXH, CLREX. These fault if no local monitor (is IMP
DEF). LDREXD and STREXD are not included in this
profile.
B, BL, and B<cond>. No BLX (1) because it always
changes state. No BXJ.
MSR(2) and MRS(2) replace MSR/MRS but also do more.
These access the other stacks and also the status registers.
CPSIE/CPSID 32-bit forms are not supported.
No RFE or SRS.
CPSIE and CPSID are quick versions of MSR(2)
instructions and use the standard Thumb encodings, but
only permit use of i and f and not a.
NOP and YIELD (hinted NOP). No MRS (1), MSR (1), or
SUBS (PC return link).
ARM DDI 0337G
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