ARM Cortex-M3 Technical Reference Manual page 17

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ARM DDI 0337G
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ITM Integration Write Register bit assignments .................................................... 11-35
ITM Integration Read Register bit assignments .................................................... 11-36
ITM Integration Mode Control bit assignments ..................................................... 11-37
ITM Lock Status Register bit assignments ............................................................ 11-38
AHB-AP Control and Status Word Register .......................................................... 11-41
AHB-AP ID Register .............................................................................................. 11-44
ICode/DCode multiplexer ........................................................................................ 12-9
ETM block diagram ................................................................................................. 14-3
Return from exception packet encoding ................................................................ 14-12
Exception encoding for branch packet .................................................................. 14-14
Conditional branch backwards not taken ................................................................ 15-8
Conditional branch backwards taken ...................................................................... 15-9
Conditional branch forwards not taken .................................................................... 15-9
Conditional branch forwards taken .......................................................................... 15-9
Unconditional branch without pipeline stalls ......................................................... 15-10
Unconditional branch with pipeline stalls .............................................................. 15-10
Unconditional branch in execute aligned .............................................................. 15-11
Unconditional branch in execute unaligned .......................................................... 15-11
Example of an opcode sequence .......................................................................... 15-13
TPIU block diagram (non-ETM version) .................................................................. 17-3
TPIU block diagram (ETM version) ......................................................................... 17-4
Supported Sync Port Size Register bit assignments ............................................. 17-10
Async Clock Prescaler Register bit assignments .................................................. 17-10
Selected Pin Protocol Register bit assignments ................................................... 17-11
Formatter and Flush Status Register bit assignments .......................................... 17-12
Formatter and Flush Control Register bit assignments ......................................... 17-13
Integration Test Register-ITATBCTR2 bit assignments ........................................ 17-15
Integration Test Register-ITATBCTR0 bit assignments ........................................ 17-16
Integration Mode Control Register bit assignments .............................................. 17-16
Integration Register : TRIGGER bit assignments ................................................. 17-17
Integration register : FIFO data 0 bit assignments ................................................ 17-18
Integration register : FIFO data 1 bit assignments ................................................ 17-19
Dedicated pin used for TRACESWO .................................................................... 17-21
SWO shared with TRACEPORT ........................................................................... 17-22
SWO shared with JTAG-TDO ............................................................................... 17-22
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