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Application Specific Standard Part/Product (ASSP)
Architecture
ARM instruction
ARM state
ASIC
ASSP
ATB
ATB bridge
Base register
Base register write-back
Beat
BE-8
ARM DDI 0337G
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An integrated circuit that has been designed to perform a specific application function.
Usually consists of two or more separate circuit functions combined as a building block
suitable for use in a range of products for one or more specific application markets.
The organization of hardware and/or software that characterizes a processor and its
attached components, and enables devices with similar characteristics to be grouped
together when describing their behavior, for example, Harvard architecture, instruction
set architecture, ARMv7-M architecture.
An instruction of the ARM Instruction Set Architecture (ISA). These cannot be
executed by the Cortex-M3.
The processor state in which the processor executes the instructions of the ARM ISA.
The processor only operates in Thumb state, never in ARM state.
See Application Specific Integrated Circuit.
See Application Specific Standard Part/Product.
See Advanced Trace Bus.
A synchronous ATB bridge provides a register slice to facilitate timing closure through
the addition of a pipeline stage. It also provides a unidirectional link between two
synchronous ATB domains.
An asynchronous ATB bridge provides a unidirectional link between two ATB domains
with asynchronous clocks. It is intended to support connection of components with ATB
ports residing in different clock domains.
A register specified by a load or store instruction that is used to hold the base value for
the instruction's address calculation. Depending on the instruction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the
address that is sent to memory.
Updating the contents of the base register used in an instruction target address
calculation so that the modified address is changed to the next higher or lower
sequential address in memory. This means that it is not necessary to fetch the target
address for successive instruction transfers and enables faster burst accesses to
sequential memory.
Alternative word for an individual data transfer within a burst. For example, an INCR4
burst comprises four beats.
Big-endian view of memory in a byte-invariant system.
See also BE-32, LE, Byte-invariant and Word-invariant.
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Glossary
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